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CorePCIF Parameters
CorePCIF is a highly configurable core. The configuration is controlled by approximately 50 top-level parameters.
These are listed in Table 4-1 to Table 4-4 on page 39 .
General Configuration Parameters
Table 4-1 shows general configuration parameters for CorePCIF.
Table 4-1 · General Parameters
4
Name
FAMILY
MASTER
TARGET
PCI_FREQ
SLOW_READ
PCI_WIDTH
DISABLE_WDOG
DISABLE_BAROV
REMOVE_CAP_ID
Values
8 to 21
0 or 1
0 or 1
33 or 66
0 or 1
32 or 64
0 or 1
0 or 1
0 or 1
Description
Must be set to the required FPGA family:
8: SX-A
9: RTSX-S
11: Axcelerator
12: RTAX-S
14: ProASIC PLUS
15: ProASIC3
16: ProASIC3E
17: Fusion
20: IGLOO
21: IGLOOe
22: ProASIC3L
When 1, the PCI Master function with DMA controller is implemented.
When 1, the PCI Target function is implemented.
When 66, the 66 MHz bit in the PCI configuration space is set.
When 1, the core inserts either one or two wait states in all read transfers, eliminating the
requirement for internal data storage within the core. This parameter must not be set if the
FIFO recovery option is enabled.
Sets 32- or 64-bit PCI implementation.
When 1, the data transfer watchdog inside the core is disabled. The core normally includes a
transfer watchdog that will terminate a PCI cycle if the backend logic fails to provide or accept
data within the time limits defined by the PCI specification. This function can be disabled in
embedded systems if longer access times are permitted.
When 1, the core will not disconnect when a memory or I/O transfer overflows the BAR as
required by the PCI specification. Instead, the core will wrap the address and jump to the
beginning of the BAR space. Setting the parameter to 1 will reduce the number of logic
elements in the core. When the BAR overflow logic is enabled, the core may disconnect burst
transfers before they reach the upper limit of the BAR, depending on the transfer rate
controlled by IRDY and TRDY. This may require the PCI Master to perform several separate
PCI transfers before the top of memory is reached.
When 1, the capability pointer and capability values in the PCI configuration space are all held
at 0. The interrupt and DMA control registers are still accessible at locations 48 and 50–5C hex.
When 0, the capability IDs are as described in Table 7-1 on page 105 and Table 7-2 on
page 106 .
v4.0
35
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